Early dual-slope analog-to-digital converters (ADC) operate with four phases: (1) the auto-zero phase, (2) the integration phase, (3) the de-integration phase, and (4) the zero-integration phase. The structure and the operation are as follows:
(1) The purpose of the auto-zero phase is to correct for the residue spurious voltage created during the integration and de-integration phases, and the offset voltage due to imperfect matching of the differential transistor pair of all the operational amplifiers in the ADC. FIG. 1 shows the block diagram of an auto-zero circuit, which includes a buffer 201, an integrator 202 and a comparator 203. With this arrangement of the buffer 201, the integrator 202 and the comparator 203, the undesirable residue spurious voltages and offset voltages can be eliminated by the capacitors 102, 103 and the resistor 101. The resistor 101 and the capacitor 103 perform the integration. Ideally, when the operational amplifier is used in the buffer, the integrator and the comparator have zero input offset voltages, a common calibrating voltage Vcom, say 0 volt, applied to the input of the buffer 201 should yield the same Vcom at the output of the comparator 203, which is connected as a voltage follower. However, due to the input offset voltage of non-ideal operational amplifiers and residue voltages during the settling time of the ADC, the output of the comparator may be different from Vcom. The error voltage due to different causes appears across the reset capacitor 102 and is stored for correcting the analog input voltage during the subsequent integration phase.
(2) FIG. 2 shows the block diagram for the integration phase, which include a buffer 301, an integrator 302 and a comparator 303. The input voltage Vin passes through the buffer 301 to the integrator for a fixed amount of time to store charges in the capacitor 401. The comparator 303 now functions as a high gain operational amplifier without any negative feedback. The correction voltage previously stored in the reset capacitor 102 is now used to cancel the errors due to any offset and residue voltages. This kind of automatic error correction technique is widely used in the ADC art.
(3) FIG. 3 shows the circuit diagram for the de-integration phase. The circuit is fed with an opposite polarity reference voltage Vref to effect de-integration. When the output of the integrator 502 returns to the initial point, say 0 volt, the comparator switches state and stops the de-integration process. If the integration time is t.sub.INT, the de-integration time t.sub.DE is related to tINT as follows: ##EQU1##
(4) FIG. 4 shows the block diagram for effecting zero integrated charge at the output of the integrator. This phase is necessary to prevent the integrator from not returning to the original state when t.sub.DE exceeds a maximum allowed time. This situation may occur when the input analog signal is excessive and represents an overflow condition. During this phase, the output of the comparator is negatively fed back to the input of the integrator to quickly reset the output of the integrator to zero. The zero integrated charge reset circuit includes an integrator 601 and a comparator 602. If the output charge does not return to the initial condition after the maximum allowed tDE, it indicates that there is an overflow of the input signal. When the overflow condition exists, the output of the comparator 602 is fed back to the input of the input of the integrator 601 to reset the output voltage of the integrator 601 back to the initial point before the first phase starts again.
From the foregoing description, it can be seen that a prior-art dual-slope ADC uses four different phases to perform two basic functions and two zero-setting functions. The two basic functions refer to the integration phase and the de-integration phase, and the two zero-setting function refers to the auto-zero phase and the zero integrated charge phase. Such a four-phase operation is time-consuming and slows down the speed of the ADC.